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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a dual 8-bit, 60 msps a/d converter ad9059 ? analog devices, inc., 1996 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram adc a t/h adc b +2.5v t/h 8 8 encode aina ainb vref v d gnd pwrdn ad9059 v dd d7a?0a d7b?0b features dual 8-bit adcs on a single chip low power: 400 mw typical on-chip +2.5 v reference and t/hs 1 v p-p analog input range single +5 v supply operation +5 v or +3 v logic interface 120 mhz analog bandwidth power-down mode: < 12 mw applications digital communications (qam demodulators) rgb & yc/composite video processing digital data storage read channels medical imaging digital instrumentation product description the ad9059 is a dual 8-bit monolithic analog-to-digital con- verter optimized for low cost, low power, small size, and ease of use. with a 60 msps encode rate capability and full-power analog bandwidth of 120 mhz typical, the component is ideal for applications requiring multiple adcs with excellent dy- namic performance. to minimize system cost and power dissipation, the ad9059 includes an internal +2.5 v reference and dual track-and-hold circuits. the adc requires only a +5 v power supply and an encode clock. no external reference or driver components are required for many applications. the ad9059s single encode input is ttl/cmos compatible and simultaneously controls both internal adc channels. the parallel 8-bit digital outputs can be operated from +5 v or +3 v supplies. a power-down function may be exercised to bring to- tal consumption to < 12 mw when adc data is not required for lengthy periods of time. in power-down mode the digital outputs are driven to a high impedance state. fabricated on an advanced bicmos process, the ad9059 is available in a space saving 28-lead surface mount plastic package (28 ssop) and is specified over the industrial (C40 c to +85 c) temperature range. customers desiring single channel digitization may consider the ad9057, a single 8-bit, 60 msps monolithic based on the ad9059 adc core. the ad9057 is available in a 20-lead sur- face mount plastic package (20 ssop) and is specified over the industrial temperature range. pin configuration 14 13 12 11 10 17 16 15 19 18 20 28 27 26 25 24 23 22 21 9 8 1 2 3 4 7 6 5 top view (not to scale) ad9059 aina v d encode gnd ainb vref pwrdn v d d7b (msb) v dd gnd gnd v dd d7a (msb) d6a d5a d4a d4b d5b d6b d3a d2a d1a d0a (lsb) d3b d0b (lsb) d1b d2b
rev. 0 C2C ad9059Cspecifications electrical characteristics ad9059brs parameter temp test level min typ max units resolution 8 bits dc accuracy differential nonlinearity +25 c i 0.75 2.0 lsb full vi 2.5 lsb integral nonlinearity +25 c i 0.75 2.0 lsb full vi 2.5 lsb no missing codes full vi guaranteed gain error 1 +25 c i C6 C2.5 +6 % fs full vi C8 +8 % fs gain tempco 1 full v 70 ppm/ c analog input input voltage range (centered at +2.5 v) +25 c v 1.0 v p-p input offset voltage +25 c i C15 0 +15 mv full vi C25 +25 mv input resistance +25 c v 150 k w input capacitance +25 cv 2 pf input bias current +25 ci 616 m a analog bandwidth +25 c v 120 mhz channel matching (a to b) gain delta +25 cv 1% fs input offset voltage delta +25 cv 4mv bandgap reference output voltage full vi 2.4 2.5 2.6 v temperature coefficient full v 10 ppm/ c switching performance maximum conversion rate full vi 60 msps minimum conversion rate full iv 5 msps aperture delay (t a ) +25 c v 2.7 ns aperture uncertainty (jitter) +25 c v 5 ps, rms output valid time (t v ) 2 full iv 4.0 6.6 ns output propagation delay (t pd ) 2 full iv 9.5 14.2 ns dynamic performance 3 transient response +25 cv 9 ns overvoltage recovery time +25 cv 9 ns signal-to-noise ratio (sinad) (with harmonics) f in = 10.3 mhz +25 c i 40 44.5 db f in = 76 mhz +25 c v 43.5 db effective number of bits f in = 10.3 mhz +25 c i 6.35 7.1 bits f in = 76 mhz +25 c v 6.9 bits signal-to-noise ratio (snr) (without harmonics) f in = 10.3 mhz +25 c i 42 46 db f in = 76 mhz +25 cv 45 db 2nd harmonic distortion f in = 10.3 mhz +25 c i C50 C62 dbc f in = 76 mhz +25 c v C54 dbc 3rd harmonic distortion f in = 10.3 mhz +25 c i C46 C60 dbc f in = 76 mhz +25 c v C54 dbc two-tone intermodulation distortion (imd) +25 c v C52 dbc channel crosstalk rejection +25 c v C50 dbc differential phase +25 c v 0.8 degrees differential gain +25 c v 1.0 % (v d = +5 v, v dd = +3 v; external reference; encode = 60 msps unless otherwise noted)
ad9059brs parameter temp test level min typ max units digital inputs logic 1 voltage full vi 2.0 v logic 0 voltage full vi 0.8 v logic 1 current full vi 1 m a logic 0 current full vi 1 m a input capacitance +25 c v 4.5 pf encode pulse width high (t eh ) +25 c iv 6.7 166 ns encode pulse width low (t el ) +25 c iv 6.7 166 ns digital outputs logic 1 voltage (v dd = +3 v) full vi 2.95 v logic 1 voltage (v dd = +5 v) full iv 4.95 v logic 0 voltage (v dd = +3 v or +5 v) full vi 0.05 v output coding offset binary code power supply v d supply current (v d = +5 v) full vi 72 92 ma v dd supply current (v dd = +3 v) 4 full vi 13 15 ma power dissipation 5, 6 full vi 400 505 mw power-down dissipation full vi 6 12 mw power supply rejection ratio (psrr) +25 c i 15 mv/v notes 1 gain error and gain temperature coefficient are based on the adc only (with a fixed +2.5 v external reference). 2 t v and t pd are measured from the 1.5 v level of the encode to the 10%/90% levels of the digital output swing. the digital output load during test is not to exceed an ac load of 10 pf or a dc current of 40 m a. 3 snr/harmonics based on an analog input voltage of C0.5 dbfs referenced to a 1.0 v full-scale input range. 4 digital supply current based on v dd = +3 v output drive with <10 pf loading under dynamic test conditions. 5 power dissipation is based on 60 msps encode and 10.3 mhz analog input dynamic test conditions (v d = +5 v 5%, v dd = +3 v 5%). 6 typical thermal impedance for the rs style (ssop) 28-pin package: q jc = 39 c/w, q ca = 70 c/w, q ja = 109 c/w. specifications subject to change without notice. ad9059 C3C rev. 0 explanation of test levels test level i C 100% production tested. ii C 100% production tested at +25 c and sample tested at specified temperatures. iii C sample tested only. iv C parameter is guaranteed by design and characteriza- tion testing. v C parameter is a typical value only. vi C 100% production tested at +25 c; guaranteed by design and characterization testing for industrial tem- perature range. absolute maximum ratings* v d , v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 v analog inputs . . . . . . . . . . . . . . . . . . . . . C0.5 v to v d + 0.5 v digital inputs . . . . . . . . . . . . . . . . . . . . . . C0.5 v to v d + 0.5 v v ref input . . . . . . . . . . . . . . . . . . . . . . . . C0.5 v to v d + 0.5 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature . . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . . C65 c to +150 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. ordering guide model temperature range package option ad9059brs C 40 c to +85 c rs-28 ad9059/pcb +25 c evaluation board warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9059 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad9059 C4C rev. 0 pin descriptions pin no. name function 1, 28 aina, ainb analog inputs for adc a and b. 2 vref internal voltage reference (+2.5 v typical); bypass with 0.1 m f to ground or overdrive with external voltage reference. 3 pwrdn power-down function select; logic high for power-down mode (digital outputs go to high- impedance state). 4, 25 v d analog +5 v power supply. 5, 24, 27 gnd ground. 6, 23 v dd digital output power supply. nominally +3 v to +5 v. 7C14 d7aCd0a digital outputs of adca. 22C15 d7bCd0b digital outputs of adcb. 26 encode encode clock for adcs a and b (adcs sample simultaneously on the rising edge of encode). table i. digital coding (vref = +2.5 v) analog input voltage level digital output 3.0 v positive full scale 1111 1111 2.502 v midscale + 1/2 lsb 1000 0000 2.498 v midscale C 1/2 lsb 0111 1111 2.0 v negative full scale 0000 0000 n n + 3 n + 5 n + 1 n + 2 n + 4 t a t v t pd t eh t el n ?3 n ?2 n ?1 n n + 1 n + 2 encode ain digital outputs t a t eh t el t v t pd aperture delay pulse width high pulse width low output valid time output prop delay 6.7ns 6.7ns 4.0ns 2.7ns 6.6ns 9.5ns 166ns 166ns 14.2ns min typ max figure 1. timing diagram pin configuration 14 13 12 11 10 17 16 15 19 18 20 28 27 26 25 24 23 22 21 9 8 1 2 3 4 7 6 5 top view (not to scale) ad9059 aina v d encode gnd ainb vref pwrdn v d d7b (msb) v dd gnd gnd v dd d7a (msb) d6a d5a d4a d4b d5b d6b d3a d2a d1a d0a (lsb) d3b d0b (lsb) d1b d2b
ad9059 C5C rev. 0 frequency ?mhz 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 030 encode = 60msps analog in = 10.3mhz, ?.5dbfs sinad = 43.9db enob = 7.0 bits snr = 45.1db db figure 2. fft spectral plot 60 msps, 10.3 mhz frequency ?mhz 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 030 encode = 60msps analog in = 76mhz, ?.5dbfs sinad = 43.0db enob = 6.85 bits snr = 44.1db db figure 3. spectral plot 60 msps, 76 mhz analog input frequency ?mhz db 0 160 20 40 60 80 100 120 140 46 30 38 36 34 32 42 40 44 encode = 60msps ain = ?.5dbfs snr sinad figure 4. sinad/snr vs. ain frequency analog input frequency ?mhz db ?0 ?0 0 160 20 40 60 80 100 120 140 ?5 ?0 ?5 ?0 ?5 ?0 ?5 2nd harmonic 3rd harmonic encode = 60msps ain = ?.5dbfs figure 5. harmonic distortion vs. ain frequency frequency ?mhz db 0 ?0 ?0 030 10 20 ?0 ?0 ?0 ?0 ?0 ?0 ?0 encode = 60msps f1 in = 9.5mhz @ ?.0dbfs f2 in = 9.9mhz @ ?.0dbfs 2f1 - f2 = ?2.0dbc 2f2 - f1 = ?3.0dbc figure 6. two-tone imd encode rate ?msps db 54 24 6 5 102030405060708090 48 30 18 12 42 36 ain = 10.3mhz, ?.5dbfs snr sinad figure 7. sinad/snr vs. encode rate
ad9059 C6C rev. 0 encode rate ?msps power ?mw 600 400 250 5 102030405060708090 550 500 350 300 450 ain = 10.3mhz, ?.5dbfs v dd = +5v v dd = +3v figure 8. power dissipation vs. encode rate temperature ? c 45.5 db 45.0 41.5 ?5 90 02570 43.5 43.0 42.5 42.0 44.5 44.0 snr sinad encode = 60msps ain = 10.3mhz, ?.5dbfs figure 9. sinad/snr vs. temperature temperature ? c 0 gain error ?% ?.2 ?.8 ?5 90 02570 ?.8 ?.2 ?.4 ?.6 ?.4 ?.6 ?.0 figure 10. adc gain vs. temperature (with external +2.5 v reference) temperature ? c 10 t pd ?ns 9.5 ?5 90 02570 8.0 6.5 6.0 9.0 8.5 7.0 7.5 v dd = +5v v dd = +3v 11 12 figure 11. t pd vs. temperature/supply (+3 v/+5 v) db encode high pulse width ?ns 46 45.5 40.5 5.8 10.9 44.5 44 43.5 43 45 41 41.5 42 42.5 6.7 7.5 8.35 9.2 10 snr encode = 60msps ain = 10.3mhz, ?.5dbfs sinad figure 12. sinad/snr vs. encode pulse width analog frequency ?mhz adc gain ?db 0 ? 1 500 10 100 ? ? ? ?0 encode = 60msps ain = ?..5dbfs ? ? ? ? ? 25 20 50 200 figure 13. adc frequency response
ad9059 C7C rev. 0 applied to the vref pin to overdrive the internal voltage refer- ence for gain adjustment of up to 10% (the vref pin is inter- nally tied directly to the adc circuitry). adc gain and offset will vary simultaneously with external reference adjustment with a 1:1 ratio (a 2% or 50 mv adjustment to the +2.5 v reference varies adc gain by 2% and adc offset by 50 mv). theoretical input voltage range versus reference input voltage may be calculated from the following equations: v range (p-p) = vref/ 2.5 v midscale = vref v top-of-range = vref + v range / 2 v bottom-of-range = vref C v range / 2 the external reference should have a 1 ma minimum sink/ source current capability to ensure complete overdrive of the internal voltage reference. digital logic (+5 v/+3 v systems) the digital inputs and outputs of the ad9059 can easily be configured to interface directly with +3 v or +5 v logic systems. the encode and power-down (pwrdn) inputs are cmos stages with ttl thresholds of 1.5 v, making the inputs compat- ible with ttl, +5 v cmos, and +3 v cmos logic families. as with all high speed data converters, the encode signal should be clean and jitter free to prevent degradation of adc dynamic performance. the ad9059s digital outputs will also interface directly with +5 v or +3 v cmos logic systems. the voltage supply pins (v dd ) for these cmos stages are isolated from the analog v d voltage supply. by varying the voltage on these supply pins the digital output high levels will change for +5 v or +3 v sys- tems. the v dd pins are internally connected on the ad9059 die. care should be taken to isolate the v dd supply voltages from the +5 v analog supply to minimize noise coupling into the adcs. the ad9059 provides high impedance digital output operation when the adc is driven into power-down mode (pwrdn, logic high). a 200 ns (minimum) power-down time should be provided before a high impedance characteristic is required. a 200 ns power-up period should be provided to ensure accu- rate adc output data after reactivation (valid output data is available three clock cycles after the 200 ns delay). timing the ad9059 is guaranteed to operate with conversion rates from 5 msps to 60 msps. at 60 msps the adc is designed to operate with an encode duty cycle of 50%, but performance is insensitive to moderate variations. pulse width variations of up to 10% (allowing the encode signal to meet the minimum/ maximum high/low specifications) will cause no degrada- tion in adc performance (refer to figure 1 timing diagram). due to the linked encode architecture of the adcs, the ad9059 cannot be operated in a two-channel ping-pong mode. theory of operation the ad9059 combines analog devices proprietary magamp gray code conversion circuitry with flash converter technology to provide dual high performance 8-bit adcs in a single low cost monolithic device. the design architecture ensures low power, high speed, and 8-bit accuracy. the ad9059 provides two linked adc channels that are clocked from a single encode input (refer to block diagram). the two adc channels simultaneously sample the analog in- puts (aina and ainb) and provide non-interleaved parallel digital outputs (d0aCd7a and d0bCd7b). the voltage refer- ence (vref) is internally connected to both adcs so channel gains and offsets will track if external reference control is desired. the analog input signal is buffered at the input of each adc channel and applied to a high speed track-and-hold. the t/h circuit holds the analog input value during the conversion pro- cess (beginning with the rising edge of the encode com- mand). the t/hs output signal passes through the gray code and flash conversion stages to generate coarse and fine digital representations of the held analog input level. decode logic combines the multistage data and aligns the 8-bit word for strobed outputs on the rising edge of the encode command. the magamp/flash architecture of the ad9059 results in three pipeline delays for the output data. using the ad9059 analog inputs the ad9059 provides independent single-ended high imped- ance (150 k w ) analog inputs for the dual adcs. each input requires a dc bias current of 6 m a (typical) centered near +2.5 v ( 10%). the dc bias may be provided by the user or may be derived from the adcs internal voltage reference. figure 14 shows a low cost dc bias implementation allowing the user to capacitively couple ac signals directly into the adc without ad- ditional active circuitry. for best dynamic performance the vref pin should be decoupled to ground with a 0.1 m f capaci- tor (to minimize modulation of the reference voltage), and the bias resistor should approximately 1 k w . figure 15 shows typical connections for high performance dc bi- asing using the adcs internal voltage reference. all compo- nents may be powered from a single +5 v supply (example analog input signals are referenced to ground). voltage reference a stable and accurate +2.5 v voltage reference is built into the ad9059 (vref). the reference output is used to set the adc gain/offset and can provide dc bias for the analog input signals. the internal reference is tied to the adc circuitry through a 800 w internal impedance and is capable of providing 300 m a external drive current (for dc biasing the analog input or other user circuitry). some applications may require greater accuracy, improved tem- perature performance, or gain adjustments which cannot be ob- tained using the internal reference. an external voltage may be
ad9059 C8C rev. 0 power dissipation the power dissipation of the ad9059 is specified to reflect a typical application setup under the following conditions: en- code is 60 msps, analog input is C0.5 dbfs at 10.3 mhz, v d is +5 v, v dd is +3 v, and digital outputs are loaded with 7 pf typical (10 pf maximum). the actual dissipation will vary as these conditions are modified in user applications. figure 8 shows typical power consumption for the ad9059 versus adc encode frequency and v dd supply voltage. 28 1 3 1k w 1k w aina ainb v ref ad9059 0.1? 0.1? 0.1? +5v vin a (1v p-p) external v ref (optional) vin b (1v p-p) figure 14. capacitively coupled ad9059 a power-down function allows users to reduce power dissipa- tion when adc data is not required. a ttl/cmos high signal (pwrdn) shuts down portions of the dual adc and brings total power dissipa tion to less than 10 mw. the internal bandgap voltage refer ence remains active during power-down mode to minimize adc reactivation time. if the power-down function is not desired, pin 3 should be tied to ground. both adc channels are controlled simultaneously by the pwrdn pin; they cannot be shut down or turned on independently. applications the wide analog bandwidth of the ad9059 makes it attractive for a variety of high performance receiver and encoder applica- tions. figure 16 shows the dual adc in a typical low cost i & q demodulator implementation for cable, satellite, or wireless lan modem receivers. the excellent dynamic performance of the adc at higher analog input frequencies and encode rates empowers users to employ direct if sampling techniques (refer to figure 3, spectral plot ). if sampling eliminates or simplifies analog mixer and filter stages to reduce total system cost and power. 28 1 10k w 1k w aina ainb v ref ad9059 0.1? +5v vin a vin b (?.5v to +0.5v) 10k w +5v +5v ad8041 ad8041 1k w 1k w 1k w 3 figure 15. dc coupled ad9059 (vin inverted) ad9059 bpf bpf 90 vco if in vco adc adc figure 16. i and q digital receiver the high sampling rate and analog bandwidth of the ad9059 are ideal for computer rgb video digitizer applications. with a full-power analog bandwidth of 2 the maximum sampling rate, the adc provides sufficient pixel-to-pixel transient settling time to ensure accurate 60 msps video digitization. figure 17 shows a typical rgb video digitizer implementation for the ad9059. 8 red green ad9059 blue ad9059 h-sync pll pixel clock 8 8 adc adc adc adc figure 17. rgb video encoder
ad9059 C9C rev. 0 +v d encode pwrdn d0?7 +v dd +3v to +5v 500 w +v d v ref ain digital inputs analog inputs digital outputs 800 w +v d v ref 3k w 2.5k w +2.5v voltage reference figure 18. equivalent circuits evaluation board the ad9059/pcb evaluation board provides an easy-to-use analog/digital interface for the dual 8-bit, 60 msps adc. the board includes typical hardware configurations for a variety of high speed digitization evaluations. on-board components in- clude the ad9059 (in the 28-pin ssop package), optional ana- log input buffer amplifiers, digital output latches, board timing drivers, and configurable jumpers for ac coupling, dc coupling, and power-down function testing. the board is configured at shipment for dc coupling using the ad9059s internal reference. for dc coupled analog input applications, amplifiers u3 and u4 are configured to operate as unity gain inverters with adjustable offset for the analog input signals. for full-scale adc drive each analog input signal should be 1 v p-p into 50 w referenced to ground. each amplifier offsets its analog signal by +vref (+2.5 v typical) to center the voltage for proper adc input drive. for dc coupled operation, connect e7 to e9 (analog in- put a to r11), e14 to e13 (amplifier output to analog input a of ad9059), e4 to e5 (analog input b to r10), and e11 to e10 (amplifier output to analog input b of ad9059) using the board jumper connectors. for ac coupled analog input applications, amplifiers u3 and u4 are removed from the analog signal paths. the analog signals are coupled through capacitors c11 and c12, each terminated to the vref voltage through separate 1 k w resistors (providing bias current for the ad9059 analog inputs, aina and ainb). analog input signals to the board should be 1 v p-p into 50 w for full-scale adc drive. for ac coupled operation, connect e7 to e8 (analog input a to c12 feedthrough capacitor), e13 to e15 (c12 to r15 termination resistor for channel a), e4 to e6 (analog input b to c11 feedthrough capacitor), and e10 to e12 (c11 to r14 termination resistor for channel b) using the board jumper connectors. the on-board reference voltage may be used to drive the adc or an external reference may be applied. the standard configu- ration employs the internal voltage reference without any exter- nal connection requirements. an external voltage reference may be applied at board connector input ref to overdrive the lim- ited current output of the ad9059s internal voltage reference. the external voltage reference should be +2.5 v typical. the power-down function of the ad9059 can be exercised through a board jumper connection. connect e2 to e1 (+5 v to pwrdn) for power-down mode operation. for normal op- eration, connect e3 to e1 (ground to pwrdn). the encode signal source should be ttl/cmos compatible and capable of driving a 50 w termination. the digital outputs of the ad9059 are buffered through latches on the evaluation board (u5 and u6) and are available for the user at connector pins 30C37 and pins 22C29. latch timing is derived from the adc encode clock and a digital clocking signal is provided for the board user at connector pins 2 and 21.
ad9059 C10C rev. 0 12 13 14 15 16 17 18 19 9 8 7 6 5 4 3 2 ck oe 1 11 u5 74acq574 8d 7d 6d 5d 4d 3d 2d 1d 8q 7q 6q 5q 4q 3q 2q 1q d0b d1b d2b d3b d4b d5b d6b d7b db0 db1 db2 db3 db4 db5 db6 db7 12 13 14 15 16 17 18 19 9 8 7 6 5 4 3 2 ck oe 1 11 u6 74acq574 8d 7d 6d 5d 4d 3d 2d 1d 8q 7q 6q 5q 4q 3q 2q 1q d7a d6a d5a d4a d3a d2a d1a d0a da7 da6 da5 da4 da3 da2 da1 da0 1 2 3 4 5 6 u7 74ac00 12 13 11 r15 50 w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 +5v +5v e10 e3 e11 c12 0.1? e14 e15 e13 pwrdn +5v e1 e2 e12 r5 10 w r14 1k w 8 7 6 5 dis +v s nc nc ? s u4 ad8041q 1 2 3 4 r11 1k w e8 r13 50 w bnc j5 analog in? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 p2 c37drpf r7 1k w bnc j10 encode j12, gnd c14 0.1? c7 0.1? c6 0.1? c15 10? c13 0.1? c5 0.1? c4 0.1? c3 0.1? +5v decoupling caps j11, v d e7 e9 u1 ad9059rs aina ref pwrdn gnd v d v dd d7a d6a d5a d4a d3a d2a d1a d0a ainb gnd enc gnd v d v dd d7b d6b d5b d4b d3b d2b d1b d0b d7b d6b d5b d4b d3b d2b d1b d0b c8 0.1? c16 10? j9, v dd c9 0.1? db0 db1 db2 db3 db4 db5 db6 db7 da0 da1 da2 da3 da4 da5 da6 da7 u7 74ac00 u7 74ac00 c10 0.1? c17 10? r9 10k w r8 10k w r15 1k w j1, ref d7a d6a d5a d4a d3a d2a d1a d0a r4 10 w 8 7 6 5 dis +v s nc nc ? s u3 ad8041q 1 2 3 4 r10 1k w e5 r12 50 w bnc j4 analog in? r8 1k w e4 e6 +5v c11 0.1? +5v figure 19. ad9059 dual evaluation board schematic
ad9059 C11C rev. 0 figure 20. evaluation board layout (top) figure 21. evaluation board layout (bottom)
ad9059 C12C rev. 0 c2160C10C7/96 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 28-lead ssop (rs-28) 28 15 14 1 0.407 (10.34) 0.397 (10.08) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 8 0

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